It is well known to utilize a multiplex digital data transfer bus to transfer data between a plurality of digital devices where any one of several of the devices can acquire use of the bus to the temporary exclusion of the other devices. Various priority assigning circuits have been devised to determine in which order competing devices will be assigned to the multiplexed bus. Some devices use a central priority control for assigning priority in a predetermined fixed order. Generally such circuits assign priority on a first come, first serve basis with a fixed sequential order being provided for resolving simultaneous requests. In one prior art scheme, a pulse is propagated along a line serially connecting all of the devices in a closed loop. As the pulse is propagated into and out of each of the devices in sequence, that device is given priority. Once the pulse reaches a device which is requesting access to the bus, propagation of the pulse is interrupted until the access is completed. In the closed loop system, initial conditions become a problem to avoid having more than one device receiving and passing along priority at the same time. In other systems priority pulses are issued by a central control. If the pulse is initiated from a central control, a fixed time must be allowed corresponding to the worst case for a priority pulse to arrive at the most distant device before another priority pulse is initiated. Therefore propagation time and the relative location of the devices becomes an important factor.